ASE Group Expands Panel-Level Packaging Lines for Oversized AI Accelerator Modules

The physical dimensions of high-performance artificial intelligence accelerator packages have rapidly outgrown the surface area limits of traditional round 300mm semiconductor wafers. To lower production costs and accommodate massive multi-die assemblies containing multiple compute chiplets and high-bandwidth memory stacks, advanced packaging foundries have accelerated the commercial transition to rectangular Panel-Level Packaging (PLP).

which suffer from geometric edge waste when

Unlike circular silicon wafers—which suffer from geometric edge waste when dicing large square or rectangular package substrates—large rectangular glass or organic panels (such as 515mm x 510mm formats) allow packaging engineers to fabricate dozens of oversized multi-chip modules simultaneously with significantly higher material utilization efficiency. This geometric advantage translates directly into lower unit manufacturing costs for hyperscale enterprise hardware.

ASE Group: Scaling to panel-level formats introduced

Scaling to panel-level formats introduced unique mechanical and optical challenges, particularly regarding substrate warpage during high-temperature thermal compression bonding and lithographic alignment distortion across expansive panel surfaces. Packaging equipment specialists deployed advanced laser direct imaging (LDI) tools and specialized stiffener materials to maintain sub-micron alignment precision throughout the manufacturing sequence.

Early commercial production runs confirm that?

Early commercial production runs confirm that panel-level packaging delivers exceptional yield stability for complex heterogeneous packages. As AI processor physical sizes continue to scale upward to integrate more compute tiles and optical engines, panel-level manufacturing has established itself as an indispensable pillar of advanced semiconductor fabrication.