Bandwidth is the real bottleneck.

SK Hynix Expands Advanced Packaging Footprint with Dedicated High-Bandwidth Memory Assembly Plant

SK Hynix has broken ground on a specialized advanced packaging facility designed exclusively for next-generation High-Bandwidth Memory integration, aiming to alleviate supply constraints for AI accelerators.

Micron

Micron Technology Begins Volume Production of Next-Gen Low-Power Memory for Mobile AI Handsets

Micron Technology has initiated commercial volume shipments of its newest ultra-fast mobile memory modules, optimized to feed high-bandwidth data to generative AI models running on smartphones.

Intel

High-Density Silicon Bridge Packaging Eliminates Interposer Bottlenecks in Hyperscale AI Accelerators

Advanced packaging engineers have scaled up embedded multi-die interconnect bridge manufacturing to link multiple compute and memory chiplets without the yield risks of large silicon interposers.

Intel

UCIe Consortium Ratifies Standardized Die-to-Die Protocol for Multi-Vendor Chiplet Ecosystems

The Universal Chiplet Interconnect Express consortium has officially released updated protocol specifications enabling seamless die-to-die communication across disparate foundry nodes.

Samsung

HBM4 Memory Architecture Integrates Custom Logic Die to Support Custom AI Accelerators

Samsung Memory has detailed its upcoming HBM4 specifications, featuring a dedicated foundry-manufactured base die that replaces traditional buffer logic for enhanced bandwidth.

ASE Group

ASE Group Expands Panel-Level Packaging Lines for Oversized AI Accelerator Modules

Advanced packaging foundries are ramping up rectangular panel-level packaging capacity to process oversized multi-die substrates more efficiently than traditional round 300mm silicon wafers.

TSMC

Embedded MRAM Integration Advances Non-Volatile Microcontroller Performance for Edge AI

Foundry deployment of embedded magnetoresistive random-access memory provides high-speed, non-volatile data storage with zero standby power consumption for edge artificial intelligence microcontrollers.

SK Hynix

Direct Cu-Cu Hybrid Bonding Eliminates Micro-Bumps in High-Bandwidth Memory Stacks

Memory manufacturers are deploying direct copper-to-copper hybrid bonding to connect dynamic RAM die layers without solder micro-bumps, reducing vertical profile and thermal resistance.

Interface Silicon · 2026-09-02

Marvell

CXL 3.1 Memory Pooling Controllers Unlock Low-Latency Fabric Expansion for AI Data Centers

Silicon developers have taped out advanced Compute Express Link controllers that enable pooled server memory sharing across rack-scale fabrics with near-native DRAM latency.