As gate-all-around nanosheet transistor scaling nears its physical and geometric limits, semiconductor research consortia are aggressively advancing monolithic complementary field-effect transistor (CFET) architectures. Recent fabrication trials conducted by collaborative foundry teams have demonstrated successful vertical stacking of nMOS devices directly on top of pMOS channels, effectively folding standard cell footprints in half and breaking through traditional density walls.
In conventional planar or fin-based complementary
In conventional planar or fin-based complementary metal-oxide-semiconductor layouts, nMOS and pMOS transistors are placed side-by-side on the silicon substrate, requiring considerable separation space to satisfy isolation and well-tap rules. The CFET paradigm eliminates this lateral footprint penalty by aligning the n-type and p-type channels vertically in a single monolithic column sharing a common gate structure. This three-dimensional integration style drastically reduces wire length and routing congestion across standard cell libraries.
imec: Realizing a functional CFET required
Realizing a functional CFET required overcoming extreme manufacturing hurdles, particularly regarding selective vertical etching, dual work-function metal gate deposition, and alignment precision between the upper and lower channel tiers. Process engineers utilized advanced atomic layer deposition and directional etching techniques to isolate the stacked channels without introducing parasitic leakage currents.
Industry roadmaps indicate that CFET technology?
Industry roadmaps indicate that CFET technology will serve as the primary foundational architecture for logic scaling beyond the 1nm milestone. By maximizing active silicon utilization per square millimeter of die area, CFET structures ensure that microprocessors continue to deliver density and performance gains well into the next decade.
"Imec and leading logic foundries have successfully fabricated complementary field-effect transistors, stacking nMOS and pMOS devices vertically to double standard cell layout density." — EE Times