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Semiconductor Equipment Published 2026-09-02 Filed by Rivento editorial

Applied Materials Introduces Atomic Layer Deposition System for Gate-All-Around Transistor Manufacturing

Applied Materials has announced a specialized atomic layer deposition manufacturing tool designed to deposit uniform dielectric films required for sub-2nm gate-all-around transistor geometries.

Applied Materials Introduces Atomic Layer Deposition System for Gate-All-Around Transistor Manufacturing

The semiconductor industry is entering an era in which the most important breakthroughs are often hidden inside the layers between a transistor and a finished system. This briefing examines what this development means, why it matters now, and which signals will determine its lasting value.

As logic device architecture transitions definitively from

As logic device architecture transitions definitively from FinFET to Gate-All-Around (GAA) nanosheet structures, the atomic-scale precision required during film deposition has reached unprecedented levels of difficulty. Applied Materials has introduced a breakthrough atomic layer deposition (ALD) production system engineered specifically to coat vertical silicon nanosheets with uniform, defect-free high-k dielectric gate stacks.

In a GAA transistor, the gate material must wrap

In a GAA transistor, the gate material must wrap entirely around each suspended horizontal nanosheet channel. If the deposition film thickness varies by even a fraction of a nanometer across the channel perimeter, electrical performance degrades, leading to threshold voltage shifts and increased leakage current. The new equipment utilizes pulsed precursor gas injections inside an ultra-clean vacuum chamber, allowing chemical reactions to occur strictly on a self-limiting monolayer basis.

Applied Materials: Fabrication engineers working with early

Fabrication engineers working with early tool deployments highlight the system's advanced plasma source integration, which directs reactive species uniformly into deep, high-aspect-ratio channel gaps without causing plasma-induced physical damage to fragile silicon structures. In-situ metrology sensors monitor film thickness and composition in real-time, feeding adjustment parameters back into the deposition cycle before the wafer moves to subsequent etching stations.

Equipment market observers emphasize that capital?

Equipment market observers emphasize that capital expenditure in leading-edge semiconductor fabrication is increasingly driven by materials engineering innovations rather than lithography alone. As feature sizes shrink below the two-nanometer threshold, the ability to deposit and modify materials one atomic layer at a time determines whether foundry clients can achieve commercially viable yields on advanced logic nodes.