A calmer view of a fast industry
Where silicon
becomes intelligence.
Rivento follows the process breakthroughs, packaging shifts, and quiet infrastructure decisions shaping the next era of AI hardware.
Lead storyTSMC 2nm Nanosheet Production Line Achieves Record High Initial Yields Ahead of Major Client Shipments
Taiwan Semiconductor Manufacturing Company (TSMC) has successfully stabilized its 2nm GAAFET manufacturing process, reporting initial wafer sorting yields that surpass internal forecasts and outpace previous node introductions at similar lifecycle stages.
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Latest from the silicon stack
50 original briefings across the technologies that make modern AI possible.
AI ProcessorsAMD Unveils Multi-Die AI Accelerator Architecture Featuring Advanced Interposer Integration and Liquid Cooling
Advanced Micro Devices has detailed its upcoming enterprise AI processor architecture, utilizing a modular multi-die design and integrated liquid cooling headers to sustain high clock frequencies under continuous datacenter loads.
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Edge Computing & NPUQualcomm Expands Edge AI Silicon Lineup with NPU-Centric Architecture for Automotive and IoT Platforms
Qualcomm Technologies has introduced a new family of system-on-chips featuring dedicated neural processing units engineered for high-throughput, low-latency machine learning inference at the network edge.
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Semiconductor EquipmentApplied Materials Introduces Atomic Layer Deposition System for Gate-All-Around Transistor Manufacturing
Applied Materials has announced a specialized atomic layer deposition manufacturing tool designed to deposit uniform dielectric films required for sub-2nm gate-all-around transistor geometries.
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Memory ArchitectureMicron Technology Begins Volume Production of Next-Gen Low-Power Memory for Mobile AI Handsets
Micron Technology has initiated commercial volume shipments of its newest ultra-fast mobile memory modules, optimized to feed high-bandwidth data to generative AI models running on smartphones.
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Foundry & ManufacturingSamsung Electronics Unveils Back-Side Power Delivery Network Strategy for 1.4nm Foundry Node
Samsung Foundry has outlined its technical roadmap for implementing back-side power delivery network technology, aiming to eliminate voltage droop and routing congestion in sub-2nm chip designs.
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Instruction Set ArchitectureArm Architecture Introduces Scalable Matrix Extension Profiles for Next-Generation Edge Accelerators
Arm has detailed new hardware instruction set extensions designed to accelerate vector and matrix math workloads directly on power-constrained mobile and embedded processors.
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Electronic Design AutomationSynopsys and Ansys Deliver Integrated Silicon-Photonics EDA Platform for Optical Interconnect Design
A comprehensive electronic design automation platform has been launched to simulate electrical, thermal, and optical behaviors concurrently for co-packaged optical silicon chips.
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Power SemiconductorsInfineon Expands Wide-Bandgap Power Semiconductor Production for Industrial AI Data Centers
Infineon Technologies has inaugurated a high-volume manufacturing line for silicon carbide and gallium nitride power switches, targeting efficient energy delivery in modern AI server racks.
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Electronic Design AutomationCadence Design Systems Releases AI-Driven Layout Optimization Tool for Sub-2nm Standard Cells
Cadence has launched a machine-learning-powered placement and routing engine designed to optimize standard cell layouts and minimize parasitic capacitance on advanced nodes.
Explore story →Western Technology Consortium Develops Cryogenic CMOS Control Circuits for Quantum Computing Interconnects
A joint research group has successfully fabricated cryogenic complementary metal-oxide-semiconductor control circuits capable of operating at near-absolute-zero temperatures inside dilution refrigerators.
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Advanced SubstratesIntel Pioneers Glass Core Substrate Pilot Line for Next-Generation Multi-Die AI Accelerators
Intel Foundry has advanced its glass core substrate manufacturing initiative into pilot production, offering a viable replacement for organic laminates to eliminate warpage and support ultra-dense multi-chip module packaging.
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Silicon PhotonicsTSMC Integrates Laser Sources Directly onto Silicon Photonics Wafers for Optical Datacenter Links
TSMC has successfully integrated heterogeneous laser diodes directly onto silicon photonics fabrication lines, streamlining the manufacturing of optical transceiver chips for high-speed AI cluster communication.
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Lithography EquipmentASML Validates Carbon Nanotube Pellicles to Protect High-NA EUV Photomasks Under Extreme Thermal Loads
ASML has completed initial durability trials for advanced carbon nanotube pellicle membranes designed to shield extreme ultraviolet photomasks from debris contamination without absorbing excessive exposure energy.
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Neuromorphic ComputingNeuromorphic Silicon Architecture Achieves Real-Time Event-Based Processing for Autonomous Robotics
Intel Labs has unveiled a scalable neuromorphic processor architecture featuring spiking neural network primitives designed to execute ultra-low-latency sensor fusion and decision-making for edge robotics.
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Thermal ManagementAdvanced Indium Solder Bonding Techniques Resolve High-Heat Dissipation Challenges in 1000W AI Accelerators
Advanced packaging specialists have perfected controlled indium solder interface bonding methods to maintain structural integrity and low thermal resistance across high-power multi-chip AI processors.
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Power SemiconductorsGallium Nitride Power Stages Revolutionize Rack-Level Power Delivery in Megawatt AI Datacenters
Power semiconductor manufacturers are deploying high-frequency gallium nitride power stages to replace traditional silicon MOSFETs, drastically improving energy conversion efficiency in dense enterprise server racks.
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Lithography EquipmentExtreme UV Pellicle Optimization Solves Reticle Contamination in High-Volume Sub-2nm Manufacturing
Semiconductor equipment consortia have validated advanced protective pellicle designs that prevent airborne particulate accumulation on EUV photomasks without inducing severe optical energy absorption.
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Electronic Design AutomationMulti-Die Interposer Routing Tools Accelerate Heterogeneous Integration for Enterprise Accelerators
Electronic design automation vendors have rolled out advanced routing engines capable of managing high-density signal distribution across complex silicon interposers in multi-chip packages.
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Specialized SiliconCryogenic Packaging Innovations Enable Scalable Control Electronics for Quantum Processor Arrays
Joint engineering teams have developed specialized packaging methods for cryogenic control ASICs, allowing electronic multiplexing hardware to operate directly inside dilution refrigerators.
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Semiconductor EquipmentAdvanced Metrology Systems Deploy In-Situ X-Ray Diffraction to Monitor Nanosheet Profile Uniformity
Metrology equipment manufacturers are integrating inline x-ray diffraction inspection tools into advanced fabrication lines to measure atomic-scale structural variations in gate-all-around transistors.
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Advanced PackagingHigh-Density Silicon Bridge Packaging Eliminates Interposer Bottlenecks in Hyperscale AI Accelerators
Advanced packaging engineers have scaled up embedded multi-die interconnect bridge manufacturing to link multiple compute and memory chiplets without the yield risks of large silicon interposers.
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Semiconductor EquipmentExtreme UV Stochastic Inspection Tools Identify Sub-Nanometer Resist Defects Prior to Etching
Metrology equipment developers have deployed advanced electron-beam and computational inspection platforms designed to detect probabilistic stochastics in extreme ultraviolet photoresists.
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Foundry & ManufacturingBackside Power Distribution Networks Validate Sub-1.8nm Logic Scaling and Voltage Stability
Leading logic foundries have successfully completed electrical validation test chips utilizing backside power delivery, proving significant reductions in IR drop and signal routing congestion.
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Semiconductor EquipmentAtomic Layer Etch Precision Unlocks Damage-Free Gate-All-Around Nanosheet Channel Release
Equipment innovators have refined selective atomic layer etching systems to remove sacrificial silicon-germanium layers cleanly during gate-all-around nanosheet channel release without sidewall damage.
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Thermal ManagementLiquid-Metal Thermal Interface Materials Sustain High Heat Flux in Enterprise AI Workstations
Thermal engineering specialists have qualified gallium-indium liquid metal alloys for mass production, providing superior thermal conductivity for direct-die cooling in enterprise AI hardware.
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Advanced PackagingUCIe Consortium Ratifies Standardized Die-to-Die Protocol for Multi-Vendor Chiplet Ecosystems
The Universal Chiplet Interconnect Express consortium has officially released updated protocol specifications enabling seamless die-to-die communication across disparate foundry nodes.
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Material ScienceTwo-Dimensional Transition Metal Dichalcogenides Open Path to Sub-1nm Transistor Channels
Researchers have successfully fabricated field-effect transistors using atomic-thin transition metal dichalcogenides, overcoming silicon quantum tunneling limits.
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Memory ArchitectureHBM4 Memory Architecture Integrates Custom Logic Die to Support Custom AI Accelerators
Samsung Memory has detailed its upcoming HBM4 specifications, featuring a dedicated foundry-manufactured base die that replaces traditional buffer logic for enhanced bandwidth.
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Specialized SiliconAnalog In-Memory Computing Arrays Deliver Breakthrough Efficiency for Edge Transformer Models
Analog in-memory computing architectures are scaling into commercial production, executing matrix-vector multiplications directly inside non-volatile memory crossbar arrays.
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Semiconductor EquipmentEUV Reticle Inspection Systems Deploy Multi-Beam Electron Optics for Defect Localization
Advanced mask inspection tools utilizing multi-beam electron optics have entered foundry operation, accelerating defect identification on extreme ultraviolet photomasks.
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Silicon PhotonicsAyar Labs and Enterprise Partners Deploy Optical I/O Chiplets to Break Rack-Level Bandwidth Limits
Optical I/O chiplet architectures are transitioning from research prototypes into commercial data center deployments, replacing high-speed electrical SerDes to link massive AI clusters.
Explore story →ASE Group Expands Panel-Level Packaging Lines for Oversized AI Accelerator Modules
Advanced packaging foundries are ramping up rectangular panel-level packaging capacity to process oversized multi-die substrates more efficiently than traditional round 300mm silicon wafers.
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Electronic Design AutomationSiemens EDA Introduces Machine-Learning DRC Engine for Sub-2nm Design Verification
Electronic design automation platforms have integrated machine-learning-driven design rule checking engines to navigate the exponential verification complexity of sub-2nm semiconductor layouts.
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Memory ArchitectureEmbedded MRAM Integration Advances Non-Volatile Microcontroller Performance for Edge AI
Foundry deployment of embedded magnetoresistive random-access memory provides high-speed, non-volatile data storage with zero standby power consumption for edge artificial intelligence microcontrollers.
Explore story →Lasertec Unveils Actinic EUV Patterned Mask Inspection System for Sub-1.5nm Reticles
Advanced metrology equipment manufacturers have introduced actinic extreme ultraviolet patterned mask inspection tools, utilizing 13.5nm light directly to detect subsurface phase defects on sub-1.5nm reticles.
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Foundry & ManufacturingComplementary FET (CFET) Architecture Achieves Monolithic Vertical Stacking for Sub-1nm Logic
Imec and leading logic foundries have successfully fabricated complementary field-effect transistors, stacking nMOS and pMOS devices vertically to double standard cell layout density.
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Lithography EquipmentHigh-NA EUV Lithography Scanners Enter Full-Scale Production Lines for Sub-1.5nm Nodes
Semiconductor foundries have officially integrated high-numerical aperture extreme ultraviolet systems into high-volume manufacturing lines, achieving unprecedented critical dimension control below 1.5nm.
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Advanced PackagingDirect Cu-Cu Hybrid Bonding Eliminates Micro-Bumps in High-Bandwidth Memory Stacks
Memory manufacturers are deploying direct copper-to-copper hybrid bonding to connect dynamic RAM die layers without solder micro-bumps, reducing vertical profile and thermal resistance.
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Semiconductor EquipmentAtomic Layer Deposition Breakthrough Enables Pinpoint High-K Dielectric Uniformity on Nanosheets
Semiconductor equipment developers have refined atomic layer deposition chambers to coat complex gate-all-around nanosheet channels with atomic precision and zero pinhole defects.
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Interface SiliconCXL 3.1 Memory Pooling Controllers Unlock Low-Latency Fabric Expansion for AI Data Centers
Silicon developers have taped out advanced Compute Express Link controllers that enable pooled server memory sharing across rack-scale fabrics with near-native DRAM latency.
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Semiconductor EquipmentSub-Nanometer Gate-All-Around Spacer Etch Optimization Enhances Parasitic Capacitance Control
Advanced selective etching systems have mastered inner-spacer recess control for gate-all-around transistors, effectively suppressing parasitic gate-to-source capacitance.
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Silicon PhotonicsSuperconducting Single-Photon Detectors Integrated into Silicon Photonic Wafers for Quantum Networks
Researchers have successfully integrated superconducting nanowire single-photon detectors directly onto silicon photonic circuits, advancing scalable optical quantum networking.
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Material ScienceCarbon-Based Interconnect Dielectrics Lower RC Delay in Advanced Backend-of-Line Stacks
Semiconductor materials researchers have validated ultra-low-k carbon-doped dielectric films to minimize signal propagation delays across dense multi-layer copper interconnects.
Explore story →Multi-Die Thermal Simulation Engines Predict Dynamic Hotspot Formation in 2000W AI Processors
Electronic design automation platforms now feature real-time multi-physics thermal simulation engines capable of mapping transient temperature spikes across heterogeneous multi-chip modules.
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Foundry & ManufacturingMonolithic 3D Integration Combines Logic and Non-Volatile Memory for Ultra-Dense Edge SoCs
Foundry R&D teams have achieved monolithic three-dimensional stacking of resistive memory directly atop logic circuits, drastically shrinking the footprint of edge intelligence processors.
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